For certain applications, such as through-silicon stacking (TSS) memory-on-logic, it may be desirable to have two memory elements mounted side-by-side on a semiconductor device, two dynamic random access memory (DRAM) dies on an application specific integrated circuit (ASIC), for example, in order to improve overall capacity. Various other types of memory (random access memory (RAM), static RAM (SRAM), phase-change RAM (PRAM), magnetic RAM (MRAM), etc.) could be used in other applications and mounted in a similar manner.
Wide I/O DRAM dies for stacked applications are often configured as mono-die, for availability and cost. High capacity wide I/O DRAM dies may have edges that are about 8-12 mm long. Placing two of these dies on an ASIC that is also about 8-12 mm on each side presents mechanical difficulties because large portions of the DRAM dies extend, unsupported, over the edges of the ASIC. Further, the electrical interface on the DRAM may not intersect the ASIC.
FIG. 1 illustrates a conventional mounting arrangement and depicts a semiconductor die 102 mounted on a package substrate 104 that includes a redistribution layer 106 on the side of the semiconductor die 102 opposite the package substrate 104. First and second memory elements, in this case a first DRAM 108 and a second DRAM 110, are mounted on and electrically connected to the redistribution layer 106 by microbumps 112. As will be evident from FIG. 1, and from FIG. 2 showing the first DRAM 108 and the second DRAM 110 from above, the combined area of the first and second DRAMs 108, 110 is substantially larger than the surface area of the semiconductor die 102, and thus significant portions of each of the first and second DRAMs 108, 110 extend beyond the periphery of the semiconductor die 102 and are unsupported. This configuration may be prone to mechanical failure and may be difficult to position on a substrate because the overhang of the first and second DRAMs 108, 110 extends beyond the footprint of the semiconductor die 102. In addition, such an arrangement may require relatively long routes on backside layers and may require that interfaces be placed very close to the edge of the semiconductor die 102 to accommodate the first and second DRAMs 108, 110.
Another conventional arrangement for mounting two memory elements on a semiconductor die is illustrated in FIG. 3. FIG. 3 illustrates a semiconductor die 302 mounted on a package substrate 304. An interposer 306 is mounted on the side of the semiconductor die 302 opposite the package substrate 304, and the interposer 306 has an area approximately as large as the combined areas of a first DRAM 308 and a second DRAM 310 mounted thereon. The interposer 306 provides mechanical support as well as electrical connections between the semiconductor die 302 and the first DRAM 308 and the second DRAM 310. However, the interposer 306 must have a fine interconnect pitch, and the size of the interposer 306 and the necessarily small interconnect pitch make the interposer 306 costly.
It would therefore be desirable to obtain the benefits of having two memory elements mounted on a semiconductor die while substantially avoiding the foregoing difficulties.